1. Field of the Invention
This invention generally relates to photolithographically-patterned, out-of-plane coil structures for use in integrated circuits, circuit boards and other devices.
2. Description of Related Art
Standard bonding techniques for electrically connecting integrated circuits, or chips, to a circuit board or other device include wire bonding, tab bonding, and solder-bump flip-chip bonding. FIG. 1 shows a contact pad 3 formed on a chip 2 wire bonded to a corresponding contact pad 3 formed on a substrate 1. The contact pads 3 are electrically connected, or bonded, by a wire 4. Since the chip 2 typically has tens or even hundreds of the contact pads 3, wire bonding each contact pad 3 on the chip 2 to the corresponding contact pad 3 on the substrate 1 is labor intensive, expensive and slow. Further, the contact pads 3 must be large enough to accommodate both the wire 4 and the accuracy of the wire bonding device used to create the wire bond. Therefore, the contact pads 3 are made larger than otherwise necessary to compensate for the size limitations of wire 4 and the wire bonding device.
FIG. 2 shows the contact pad 3 formed on the chip 2 tab bonded to the corresponding contact pad 3 on the substrate 1. A flexible substrate 5 having conductive lines formed on its lower surface is forced against the contact pads 3. A layer of anisotropic adhesive (not shown) is placed between the contact pads 3 and the flexible substrate 5. When the flexible substrate 5 is pressed against the contact pads 3, the anisotropic adhesive and the conductive lines formed on the flexible substrate 5 cooperate to complete the electrical connection between the contact pads 3. Like wire bonding, tab bonding suffers from yield loss and high cost. Irregularities in the heights of the contact pad 3 result in non-uniform contacting force pressing the flexible substrate 5 against the contact pads 3. The non-uniform contacting force means that some contact pads 3 will not be properly bonded to the flexible substrate 5.
Another conventional method for bonding the contact pads 3 formed on the chip 2 to the contact pads 3 formed on the substrate 1 or to some other device is solder-bump flip-chip bonding. FIG. 3 shows the chip 2 inverted with the contact pads 3 facing toward the substrate 1. The name “flip-chip” derives from the inversion of the chip 2, since the chip 2 is “flipped over” with the contacts pads 3 facing the substrate 1, in contrast to both tab bonding and wire bonding where the contact pads 3 on the chip 2 face away from the substrate 1. In standard flip-chip bonding, solder bumps 6 are formed on the contact pads 3 on the substrate 1. The electrical connection between the corresponding contact pads 3 is completed by pressing the contact pads 3 on the chip 2 against the solder bumps 6.
Flip-chip bonding is an improvement over both wire bonding and tab bonding. The relatively soft solder bumps 6 tend to permanently deform when the chip 2 is pressed down against the solder bumps 6. This deformation of the solder bumps 6 compensates for some irregularity in the heights of the contact pads 3 and any uneven contacting pressure forcing the chip 2 against the solder bumps 6.
However, flip-chip bonding does suffer from both mechanical and thermal variations in the solder bumps 6. If the solder bumps 6 are not uniform in height or if the substrate 1 is warped, contact between the contact pads 3 and the solder bumps 6 can be broken. Also, if the contacting pressure forcing the chip 2 down on the solder bumps 6 is uneven, contact between some contact pads 3 and corresponding solder bumps 6 can fail.
FIG. 4 shows a standard technique for establishing a temporary electrical contact between two devices. A probe card 7 having a plurality of probe needles 8 contacts the contact pads 3 by physically pressing the probe needles 8 against the contact pads 3. The physical contact between the probe needles 8 and the contact pads 3 creates an electrical connection between the probe needles 8 and the lines 9 formed on the substrate 1.
The probe cards 7 are generally used to create only temporary contacts between the probe needles 8 and the contact pads 3, so that the device 10 can be tested, interrogated or otherwise communicated with. The device 10 can be a matrix of display electrodes which are part of an active-matrix liquid crystal display. Testing of the devices 10, such as liquid crystal display electrode matrices, is more thoroughly described in an application JAO 34053 to the same inventor, co-filed and co-pending herewith and herein incorporated by reference.
The probe cards 7 have many more applications than only for testing liquid crystal displays. Any device 10 having numerous and relatively small contact pads 3, similar to those found on the chip 2, can be tested using the probe card 7. However, standard techniques for producing the probe card 7 are time consuming and labor-intensive. Each probe card 7 must be custom-made for the particular device 10 to be tested. Typically, the probe needles 8 are manually formed on the probe card 7. Because the probe cards 7 are custom-made and relatively expensive, the probe cards 7 are not typically made to contact all of the contact pads 3 on the device 10 at one time. Therefore, only portions of the device 10 can be communicated with, tested or interrogated at any one time, requiring the probe card 7 be moved to allow communication, testing or interrogation of the entire device 10.
The probe cards 7 are also used to test the chips 2 while the chips 2 are still part of a single-crystal silicon wafer. One such probe card 7 is formed by photolithographic pattern plated processing, as disclosed in Probing at Die Level, Corwith, Advanced Packaging, February, 1995, pp. 26-28. Photolithographic pattern plated processing produces probe cards 7 which have essentially the same design as the standard probe card 7. However, this new type of processing appears to automate the method for producing probe needles 8, thus avoiding manually forming the probe needles 8. Also, this article discloses a probe card 7 which is bent at the end nearest the probe needles 8, as shown in FIG. 5. The bend in the probe card 7 allows the probe needles 8 to contact the contact pad 3 at an angle. As the probe card 7 pushes the probe needles 8 into the contact pads 3, a mechanical scrubbing action occurs which allows the probe needles 8 to break through the oxide formed on the top surface of the contact pad 3.
All of the standard probe cards 7, however, are limited to testing contact pads 3 which are arranged in a linear array. Also, the standard probe cards 7 are sensitive to variations in the height of the contact pads 3 on the substrate 1, irregularities or warping of the substrate 1, and temperature variations.
The integration of small inductors on silicon substrates has been the subject of intense worldwide research for more than 15 years. This effort is driven by the desire to integrate coils on silicon and gallium arsenide integrated circuits (ICs). The structures proposed so far, however, have been variations of devices in which, due to technological constraints, the coil windings have almost always been implemented as spirals parallel to the underlying substrate.
These in-plane architectures have two major drawbacks. When made on a substrate that is slightly conducting such as silicon, the coil magnetic fields induce eddy currents in the underlying substrate. These currents cause resistive dissipation that contributes to the coil losses. The second problem arises when the coil is operated at high frequencies, where skin and proximity effects force the coil current to flow along the outer surfaces of the conductor. The “skin depth” is about 2 to 3 μm for typical conductors at frequencies of interest for wireless communication, for example, 900 MHz, 1.9 GHz and 2.4 GHz. The AC resistance of the coil conductor becomes appreciably higher than its DC resistance because the cross section of the conductor is not fully used.
FIG. 31 shows the current distribution in in-plane coils operated at high frequencies. Darker shading in the coil indicates a higher current density. The disk-shaped coil shown in FIG. 31a has a current distribution that is concentrated at the outer edges of the winding wire. Therefore, widening the conductor simply increases the unused portion of the conductor and does not reduce the AC resistance. This situation may be compared to the typical discrete component, out-of-plane coil of FIG. 31b, where the AC resistance can be reduced by simply making the conductors wider.
Solutions have been proposed and tried in the past to address the drawbacks associated with in-plane inductor coils. Eddy currents can be reduced, for example, by etching away the substrate underneath the coil. However, this approach is not practical as it sacrifices structural integrity and destroys existing electronic circuitry on the silicon substrate. To reduce the AC resistance of the device in FIG. 31a, the conductor can be made very thick using micromachining techniques such as LIGA (see A. Rogner et al., “The LIGA technique—what are the new opportunities,” J. Micromech. Microeng., vol. 2, pp. 133-140, 1992.). However, processing high aspect ratio structures is difficult and expensive.
Various out-of-plane techniques have been suggested. For example, Chukwunenye Stanley Nnebe, in “A Mechanically-raised Micromachined Variable Inductor Coil” (www.ee.cornell.edu/MENG/Abstracts/tien.htm) describes an out-of plane variable inductor structure. The structure is initially gold-metallized strips of polysilicon on the surface plane of the substrate, which are then raised and fastened via a hinging system to form a triangular geometry upon contact. After the setup of the coil is completed, the slider representing the magnetic core can then be activated through an impact system that is controlled by four comb-drive resonators (two comb-drive resonators for each direction of motion). The insertion of the magnetic core through the coils would influence the magnetic flux developed around the coils and, thus, would vary the inductance accordingly. The tuning range of the inductor is set by this effect, and reliable data may be obtained by carefully controlling the four resonators that actuate the slider causing it to move a finite distance through the coils. Such a technique is fairly complicated to micromachine and requires additional components on valuable chip real estate.
Robert Marcus et al. in International PCT Application number WO 99/18445 filed Oct. 2, 1998, titled Michromachined Element and Method of Fabrication Thereof, discloses a coiled structure that is formed by depositing two layers of material having different coefficients of thermal expansion on a sacrificial layer, removing the sacrificial layer, then heating the cantilevered structure until it curls partially upon itself. Coil closure is achieved by patterning a tethered end to the tip of the cantilevered structure. When the sacrificial layer is removed and the cantilever heated, the cantilever curls on itself, causing the tethered end to twist. Such a method and structure, however, is impractical for creating arrays of densely packed, integrated micro-inductors and other structures on silicon substrates.
Low-loss inductors that can be integrated on chip are most desirable in wireless communication devices such as cellular phones, pagers, GPS receivers, warehouse management RF identification tags, wireless computer LANs, personal digital assistants, and satellite telecommunication. Small portable devices, in particular, require the lowest possible power consumption for extended battery life and a maximal circuit integration to reduce device size and PC board complexity. The quest for low-loss inductors is driven by a fundamental trade-off between power consumption on one hand and the need for low-loss circuit passives (i.e. inductors and capacitors) on the other. Lowering the transistor bias in radio circuits reduces the power dissipation, but also significantly degrades amplifier gains, oscillator stability and filter selectivity. Using low-loss passives is the only viable technique to overcome this problem. Low-loss capacitors in the 0.1 to 100 pF range are routinely integrated on chip nowadays. However, state-of-the-art integrated coil architectures are still too lossy to be of use in integrated RF designs. All present RF chipsets, therefore, are limited to using discrete inductors that form a real estate bottleneck in today's increasingly miniaturized applications.
Modern wireless designs typically run in the lower GHz bands. The standard frequencies for cellular phones are 900 MHz, 1.8 GHz, 1.9 GHz and 2.4 GHZ, while 900 MHz is the frequency of choice for digital cordless phones. The 410-430 MHz, 870 MHz and 900-930 MHz bands are used for wireless RS-232, computer LANs and RF identification. At these 100 MHz to GHz frequencies, the passives of choice are typically, for inductors, 1 to 30 nH and, for capacitors, 1 to 30 pF. The intermediate frequencies in superheterodyne receivers are 40 to 350 MHz which calls for passives in the order of 100 to 1000 nH and 10 to 100 pF. Although high quality on-chip capacitors ranging from 0.1 pF to 100 pF are commonplace, integrated inductors and integrated variable capacitors that meet the low-loss requirements are currently not available.
Variable capacitors (varicaps) that can be integrated on chip are also in great demand. The benchmark architecture for contemporary wireless transceivers is still the superheterodyne architecture, which uses both inductors and varicaps. Variable capacitors are essential components of superheterodyne circuits used in many wireless devices. Superheterodyne circuits containing both inductors and capacitors currently cannot be integrated on chip in commercial devices, and so present a bottleneck to device miniaturization. The missing links in implementing full superheterodyne wireless architectures on a chip are inductors with quality factors of at least 30 to 50, variable capacitors (varicaps) with a tuning range of 10% and quality factors of 30 to 50, and oscillators with quality factors of 10,000 or more. The process technology for making the capacitors should be compatible with the process for making the inductors.
Present wireless devices use discrete off-chip components to implement superheterodyne circuits. The very high Q oscillator is usually a crystal oscillator. There are also numerous Voltage Controlled Oscillators (VCOs), each of which uses at least one discrete inductor and one discrete varicap. Because of these discrete components VCOs occupy a large portion of many RF circuit area. Being able to integrate entire VCOs on chip requires a new type of varicap as well as inductor.
There is a need for a micromachined coil structure which is easy to manufacture and does not use a lot of chip real estate. There is a need for low loss coil structures and variable capacitors that can be integrated on conductive substrates, such as silicon. There is also a need for an integrated coil structure in which the windings have lower resistance. There is a need for a method of manufacturing a coil structure in which closing the turns of the coil electrically produces a viable electrical structure. There is a need for a manufacturable technique that results in a closed coil structure suitable for high-Q integrated passive inductor elements. There is a need for a manufacturing technique which would enable the integration of both on chip inductors and varicaps.